The Pin define for P1 and P2
| P1 |
Definition |
P1 |
Definition |
|
P2 |
Definition |
P2 |
Definition |
| 1 |
PWR_SYS |
2 |
DGND |
|
1 |
DGND |
2 |
XRTCCLKO |
| 3 |
VDD_RTC_AP |
4 |
XuRXD0 |
|
3 |
XciPCLK |
4 |
XnWRESET |
| 5 |
M_nRESET |
6 |
XuTXD0 |
|
5 |
XciVSYNC |
6 |
XPWRRGTON |
| 7 |
Xmmc3CLK |
8 |
XuCTSn0 |
|
7 |
XciHREF |
8 |
XPSHOLD |
| 9 |
Xmmc3CMD |
10 |
XuRTSn0 |
|
9 |
XciDATA0 |
10 |
XEINT8 |
| 11 |
Xmmc3CDn |
12 |
XuRXD1 |
|
11 |
XciDATA1 |
12 |
XEINT10 |
| 13 |
Xmmc3DATA0/SD_2_DATA4 |
14 |
XuTXD1 |
|
13 |
XciDATA2 |
14 |
XEINT11 |
| 15 |
Xmmc3DATA1/SD_2_DATA5 |
16 |
XuCTSn1 |
|
15 |
XciDATA3 |
16 |
XEINT12 |
| 17 |
Xmmc3DATA2/SD_2_DATA6 |
18 |
XuRTSn1 |
|
17 |
XciDATA4 |
18 |
XEINT13 |
| 19 |
Xmmc3DATA3/SD_2_DATA7 |
20 |
XuRXD2 |
|
19 |
XciDATA5 |
20 |
XEINT14 |
| 21 |
Xi2sSCLK0/PCM_SCLKO |
22 |
XuTXD2 |
|
21 |
XciDATA6 |
22 |
XEINT15 |
| 23 |
Xi2sCDCLK0/PCM_EXTCLK0 |
24 |
XuCTSn2/i2cSDA3 |
|
23 |
XciDATA7 |
24 |
XEINT25 |
| 25 |
Xi2sLRCK0/PCM_FSYNC0 |
26 |
XuRTSn2/i2cSCL3 |
|
25 |
XciCLKenb |
26 |
XEINT26 |
| 27 |
Xi2sSDI0/PCM_SIN0 |
28 |
XuRXD3 |
|
27 |
XciFIELD |
28 |
XEINT27 |
| 29 |
Xi2sSDO0_0/PCM_SOUT0 |
30 |
XuTXD3 |
|
29 |
Xi2cSDA0 |
30 |
XEINT28 |
| 31 |
XpwmTOUT0 |
32 |
XspiCLK0 |
|
31 |
Xi2cSCL0 |
32 |
XEINT29 |
| 33 |
XpwmTOUT1 |
34 |
XspiCSn0 |
|
33 |
CAM_A_RESET |
34 |
Xmmc2DATA0 |
| 35 |
DGND |
36 |
XspiMISO0/i2cSDA4 |
|
35 |
CAMA_PWR_EN |
36 |
Xmmc2DATA1 |
| 37 |
i2cSDA1 |
38 |
XspiMOSI0/i2cSCL4 |
|
37 |
XspiCLK1/IEM_CLK |
38 |
Xmmc2DATA2 |
| 39 |
i2cSCL1 |
40 |
DGND |
|
39 |
XspiCSn1/IEM_DAT |
40 |
Xmmc2DATA3 |
| 41 |
XvvD0 |
42 |
XvvD1 |
|
41 |
XspiMISO1/i2cSDA5 |
42 |
Xmmc2CMD |
| 43 |
XvvD2 |
44 |
XvvD3 |
|
43 |
XspiMOSI1/i2cSCL5 |
44 |
Xmmc2CDn |
| 45 |
XvvD4 |
46 |
XvvD5 |
|
45 |
XuotgDP |
46 |
Xmmc2CLK |
| 47 |
XvvD6 |
48 |
XvvD7 |
|
47 |
XuotgDM |
48 |
DGND |
| 49 |
XvvD8 |
50 |
XvvD9 |
|
49 |
XuotgID |
50 |
XhdmiTX0P |
| 51 |
XvvD10 |
52 |
XvvD11 |
|
51 |
XuotgVBUS |
52 |
XhdmiTX0N |
| 53 |
XvvD12 |
54 |
XvvD13 |
|
53 |
XuoDRVVBUS |
54 |
XhdmiTX1P |
| 55 |
XvvD14 |
56 |
XvvD15 |
|
55 |
DGND |
56 |
XhdmiTX1N |
| 57 |
XvvD16 |
58 |
XvvD17 |
|
57 |
XuhostSTROBE1 |
58 |
XhdmiTX2P |
| 59 |
XvvD18 |
60 |
XvvD19 |
|
59 |
XuhostDATA1 |
60 |
XhdmiTX2N |
| 61 |
XvvD20 |
62 |
XvvD21 |
|
61 |
XuhostSTROBE2 |
62 |
XhdmiTXCP |
| 63 |
XvvD22 |
64 |
XvvD23 |
|
63 |
XuhostDATA2 |
64 |
XhdmiTXCN |
| 65 |
LCD_VSYNC |
66 |
LCD_HSYNC |
|
65 |
i2cSDA7 |
66 |
XEINT30/HDMI_CEC |
| 67 |
LCD_VCLK |
68 |
LCD_VDEN |
|
67 |
I2CSCL7 |
68 |
XEINT31/HDMI_HPD |
| 69 |
DGND |
70 |
BOOT_CS |
|
69 |
XadcAIN0 |
70 |
DGND |
The Pin define for P3 and P4
| P3 |
Definition |
P3 |
Definition |
|
P4 |
Definition |
P4 |
Definition |
| 1 |
VDD_SYS_3.3V |
2 |
DGND |
|
1 |
XEINT16 |
2 |
DGND |
| 3 |
XEINT0 |
4 |
XEINT1 |
|
3 |
XEINT17 |
4 |
XmipiMDP3 |
| 5 |
XEINT2 |
6 |
XEINT3 |
|
5 |
XEINT18 |
6 |
XmipiMDN3 |
| 7 |
XEINT4 |
8 |
XEINT5 |
|
7 |
XEINT19 |
8 |
XmipiMDP2 |
| 9 |
XEINT6 |
10 |
XEINT7 |
|
9 |
XEINT20 |
10 |
XmIPIMDN2 |
| 11 |
Xm0ADDR0 |
12 |
Xm0ADDR1 |
|
11 |
XEINT21 |
12 |
XmipiMDPCLK |
| 13 |
Xm0ADDR2 |
14 |
Xm0ADDR15 |
|
13 |
XEINT22 |
14 |
XmipiMDNCLK |
| 15 |
Xm0CSn2 |
16 |
XnRSTOUT |
|
15 |
XEINT23 |
16 |
XmipiMDP1 |
| 17 |
Xm0WEn |
18 |
Xm0OEn |
|
17 |
XEINT24 |
18 |
XmipiMDN1 |
| 19 |
Xm0DATA0 |
20 |
Xm0DATA1 |
|
19 |
XsbusData/SLIM_DAT |
20 |
XmipiMDP0 |
| 21 |
Xm0DATA2 |
22 |
Xm0DATA3 |
|
21 |
XsbusClk/SLIM_CLK |
22 |
XmipimdN0 |
| 23 |
Xm0DATA4 |
24 |
Xm0DATA5 |
|
23 |
XCLKOUT |
24 |
DGND |
| 25 |
Xm0DATA6 |
26 |
Xm0DATA7 |
|
25 |
DGND |
26 |
XispSPICLK |
| 27 |
Xm0DATA8 |
28 |
Xm0DATA9 |
|
27 |
XadcAIN1 |
28 |
XispSPICSn |
| 29 |
Xm0DATA10 |
30 |
Xm0DATA11 |
|
29 |
XadcAIN2 |
30 |
XispSPIMISO |
| 31 |
Xm0DATA12 |
32 |
Xm0DATA13 |
|
31 |
XadcAIN3 |
32 |
XispSPIMIOSI |
| 33 |
Xm0DATA14 |
34 |
Xm0DATA15 |
|
33 |
DGND |
34 |
DGND |
|
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